SOI Wafers - The Importance of The BOX
The electrical isolation is provided on the BOX (buried oxide) layer between the substrate and the top Silicon (SI) layer, as well as working as a diffusing barrier of metal contaminants to the top layer. Meaning contaminates in the location of the device layer, or on the wafer base side, has to diffuse through the BOX layer prior to reaching either location (see Figure 1.)
[if gte vml 1]><v:shapetype id="_x0000_t75" coordsize="21600,21600" o:spt="75" o:preferrelative="t" path="m@4@5l@4@11@9@11@9@5xe" filled="f" stroked="f"> <v:stroke joinstyle="miter"></v:stroke> <v:formulas> <v:f eqn="if lineDrawn pixelLineWidth 0"></v:f> <v:f eqn="sum @0 1 0"></v:f> <v:f eqn="sum 0 0 @1"></v:f> <v:f eqn="prod @2 1 2"></v:f> <v:f eqn="prod @3 21600 pixelWidth"></v:f> <v:f eqn="prod @3 21600 pixelHeight"></v:f> <v:f eqn="sum @0 0 1"></v:f> <v:f eqn="prod @6 1 2"></v:f> <v:f eqn="prod @7 21600 pixelWidth"></v:f> <v:f eqn="sum @8 21600 0"></v:f> <v:f eqn="prod @7 21600 pixelHeight"></v:f> <v:f eqn="sum @10 21600 0"></v:f> </v:formulas> <v:path o:extrusionok="f" gradientshapeok="t" o:connecttype="rect"></v:path> <o:lock v:ext="edit" aspectratio="t"></o:lock> </v:shapetype><v:shape id="Picture_x0020_1" o:spid="_x0000_i1025" type="#_x0000_t75" href="http://www.appliedwatts.com/#!soi-wafer-stock/eifwi" style='width:351pt; height:263.25pt;visibility:visible;mso-wrap-style:square' o:button="t"> <v:fill o:detectmouseclick="t"></v:fill> <v:imagedata src="file:///C:\Users\Owner\AppData\Local\Temp\msohtmlclip1\01\clip_image001.jpg" o:title=""></v:imagedata> </v:shape><![endif][if !vml][endif]
During this time, the contaminants that are already in the top layer have been essentially trapped and cannot be removed through what is called a gettering process in the substrate or on the base layer.
DIFFUSION ENHANCED WITH HIGH TEMPS
When the SOI wafer reaches a temperature <1050C during the manufacturing process, the diffusion process through the BOX layer plays a stronger role at these high temperatures. Newer devices are typically restricted to lower temperatures with process times that are comparatively short so that the BOX layer will be used as an operational diffusion barrier for transitional metals, excluding the fast diffusing copper (Cu).
SOI wafers used in volume production have a primary focus to precisely control metal contamination of the wafer front side and the device layer. With the limited thickness of the device layer, contamination is limited to 1 x 10¹º cm ̄², area density, trapped above the BOX translating to a bulk contamination level in the 1x10¹⁵ cm ̄³ range, which is considerably higher than the usual critical bulk contamination of 1x10¹¹ cm ̄³.
Using a SIMS TXRF, metal levels can be monitored. Or a mass spectrometry tool, chemically dissolving the SI and Oxide layers, contamination levels can be determined. The SIMS tool however can provide a depth profile and important details about the location of concentration spikes.
For more information on Applied Watts SOI wafers, please visit our website now and check out our SOI Wafer Stock.
Best Regards,
AW
