Deep Etching Silicon Wafers

Plasma materials processing have become more important as materials and chemistries have increased in difficulty with process requirements becoming increasingly rigorous.

Deep etching of silicon wafers has been required for IC fabrication and micro-machining in cases with the two most well-known processes being and Cryogenic Etching (CE) and Bosch Etching (BE) as shown below.

CE requires temperatures to be in the range of -110ºC during etching, and BE requires high density inductively coupled plasmas and uses alternating steps of isotropic etching and wall passivation.

To reduce the potential of unidirectional vertical etching in BE, there needs to be a process to protect the side walls. This is accomplished by depositing a polymer such as PTFE, which protects the side walls. The polymer is only stable at temperatures below 50ºC. The BE also requires active ions in order to break the PTFE layer at the bottom providing energy significantly increasing the etch rate.

On the CE process, the wafer is chilled and the lower temperature slows down the chemical reaction that produces isotropic etching. Upward-facing ions continue to barrage the surfaces and etch them away. The process produces highly vertical sidewall trenches, however extreme cold with etching have a tendency to crack the masks.

APPLICATIONS

Typical standard etching or, RIE, is roughly 10-20um thick for DRAM processing for example. For BE and CE, the etching can be up to 600um with rates up to 20um per minute. With these deeper etching processes higher plasma power is needed. This is particularly required with glass etch. Metal masks may be used with the caveat that you will be paying much more for the tooling. There is an option of using gallium ion implanted mask in CE which may reduce challenges defined earlier.

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Regards,

AW

Appliedwatts.com